1. Field of the Invention
This invention relates to a recording apparatus which adopts a magneto-optical recording method.
2. Description of the Related Art
In recent years, a magneto-optical disk has been put into practical use as a recording medium for music and/or data, and a system is known wherein music or data can be not only reproduced from but also recorded onto a magneto-optical disk by a user.
As a magneto-optical recording method for a magneto-optical disk, a magnetic modulation method is adopted widely.
In the case where the magnetic modulation method is adopted, as shown in FIG. 1, a recording head for a disk 91 is so constructed that an optical head 92 faces to a magnetic head 93 in such a manner as to put the disk 91 therebetween. The disk 91 has a vertically magnetized film 91a thereon. The optical head 92 includes an objective lens 94.
Upon recording operation, a laser beam is irradiated from the optical head 92 upon the vertically magnetized film 91a to raise the temperature of a recording portion of the disk 91 to a temperature (approximately 180.degree. C.) higher than the Curie temperature. Thereupon, a magnetic field of the N or S pole is applied from the magnetic head 93 to the vertically magnetized film 91a so that a magnetic pattern is recorded onto the vertically magnetized film 91a. Accordingly, recording of data onto the disk 91 is realized when the magnetic head 93 generates a magnetic field of the N or S polarity in accordance with data to be recorded.
When recording is performed in accordance with the magnetic field modulation method, if the recording signal has such a rectangular waveform as shown in FIG. 2A, the electric current flowing through a coil 93a of the magnetic head 93 has such an integration waveform having a certain time constant as seen in FIG. 2B. Meanwhile, the magnetic field produced by the magnetic head 93 has such an integration waveform substantially equal to the waveform of the electric current as seen in FIG. 2C. It is to be noted that reference character Id in FIG. 2B indicates a driving electric current and Hd indicates an intensity of the magnetic field corresponding to the driving electric current Id.
Generally, in a magneto-optical recording system in which an optical head and a magnetic head are used in this manner, the magnetic head must give a sufficient magnetic field to a range of movement of a lens of the optical head in a tracking direction.
In almost every apparatus, the range of movement of the lens in the tracking direction is a region of the diameter of 0.6 to 1 mm. Meanwhile, the magnetic head disposed in an opposing relationship to the optical head includes an E-shaped core. The E-shaped core has at a central portion thereof a rectangular parallelepiped center pole wound with a coil and at the opposite ends thereof a pair of rectangular parallelepiped side yokes which serve as side paths of a magnetic field.
The sectional area of the center pole is set so as to correspond to the diameter of 0.6 to 1 mm, which is the range of movement of the lens in the tracking direction, in order to assure a maximum efficiency. Further, in order to assure a high efficiency of a winding on the center pole, the cross section of the winding portion of the center pole is set substantially to a square shape.
It is known that, in order to reduce the resistance of the winding and assure a sufficient number of turns under the conditions described above, preferably a wire having a diameter of 50 to 100 .mu.m is wound by a winding number of 30 to 40 turns. Further, where ferrite is used as a material of the core, the coil has an inductance L of approximately 4 to 6 .mu.H and a resistance value of 0.5 to 1 .OMEGA..
Those values are substantially fixed even if the other parameters are varied. Accordingly, a driving circuit for the magnetic head can obtain sufficient characteristics in practical use by optimization with L=5 .mu.H.
In recent years, a system in which such magneto-optical disk recording apparatus is applied for music data has been put into practical use.
Recording data for driving a magnetic head undergo EFM modulation (Eight-Fourteen (8-14) modulation), and such EFM data are pulse signals which exhibits a pulse reversal interval ranging from 3 T at minimum to 11 T at maximum. The transfer rate of the EFM signal is set to a rate of T=230 nsec, and a magnetic recording operation of a magnetic head based on an EFM signal of this transfer rate is optimized.
While the transfer rate is sufficiently high for music data, a higher transfer rate is desired for recording or reproduction of, for example, data for a computer or moving picture data.
A circuit construction of a magnetic head driving system which can switchably use an ordinary transfer rate (for music applications) and a high transfer rate (for computer data or the like) is shown in FIG. 3.
Referring to FIG. 3, data such as audio data are supplied from a terminal 23 to an encoder 14. At the encoder 14, the data undergo CIRC (Cross Interleaved Reed Solomon Code) encoding, EFM modulation and some other necessary processing, to form an EFM signal.
The EFM signal is supplied to a control signal production circuit 15P. The control signal production circuit 15P includes a logic circuit 15Pa and produces and outputs control signals Sig1 to Sig6 for a magnetic head driving circuit 16 based on the EFM signal (Sig0). The magnetic head driving circuit 16 allows an electric current to flow into a coil 6L of a magnetic head 6 in response to the control signals Sig1 to Sig6 so that a magnetic field may be applied from the magnetic head 6 to a disk not shown in FIG. 3.
A clock generation section 20 generates a clock signal for operation at an ordinary transfer rate. A clock frequency variation section 21 multiplies the frequency of the clock signal from the clock generation section 20 by the number N, to produce another clock signal for operation at a high transfer rate. Either the clock signal for the ordinary rate from the clock generation section 20 or the clock signal for the high rate from the clock frequency variation section 21 is selected by a switching operation of a switch 22 in response to a switching signal Sel from a control section or a like element not shown. The selected clock signal is supplied as a processing clock signal CK to the encoder 14 and the control signal production circuit 15P.
Specifically, when the switch 22 is connected at an N terminal thereof, a recording operation is performed at the ordinary transfer rate, but when it is connected at an F terminal thereof, a recording operation is performed at the high transfer rate, for example, a rate equal to twice the ordinary transfer rate.
The magnetic head driving circuit 16 is constructed as shown in FIG. 4.
Referring to FIG. 4, the magnetic head driving circuit 16 includes switching elements SW.sub.1 to SW.sub.6 to which the control signals Sig1 to Sig6 from the control signal production circuit 15P are inputted as switching control signals, respectively.
A head terminal h.sub.1 connected to the coil 6L of the magnetic head 6 is connected to a positive dc power source 16a by way of the switching element SW.sub.1 and is grounded by way of the switching element SW.sub.5. Further, the head terminal h.sub.1 is connected to a negative dc power source 16b byway of the switching element SW.sub.3 and also byway of a diode D.sub.1.
Another head terminal h.sub.2 connected to the other end of the coil 6L of the magnetic head 6 is connected to the positive dc power source 16a by way of the switching element SW.sub.2 and is grounded by way of the switching element SW.sub.6. Further, the head terminal h.sub.2 is connected to the negative dc power source 16b by way of the switching element SW.sub.4 and also byway of a diode D.sub.2.
The potential +V of the positive dc power source 16a is set, for example, to +5 V, and the potential -V of the negative dc power source 16b is set, for example, approximately to -45 V. Further, the ground is used as a power source of the 0 V potential.
The logic circuit 15Pa of the control signal production circuit 15P which supplies the control signals Sig1 to Sig6 to the magnetic head driving circuit 16 is constructed as shown in FIG. 5 and produces the control signals Sig1 to Sig6 using the EFM signal (Sig0) and the clock signal CK.
Referring to FIG. 5, the EFM signal is supplied as the signal Sig0 to a terminal 50. Meanwhile, the clock signal CK is supplied to a terminal 57 by way of the switch 22 of FIG. 3.
The logic circuit 15Pa includes inverters IV.sub.1 to IV.sub.7, flip-flops FF.sub.1 and FF.sub.2, AND gates A.sub.1 to A.sub.7, and delay circuits DL.sub.1 and DL.sub.2. The logic circuit 15Pa has output terminals 51 to 56 for outputting the control signals Sig1 to Sig6, respectively.
Operation of the logic circuit 15Pa will be described with reference to FIGS. 6A to 6O.
It is assumed that such a signal Sig0 (EFM signal) as seen in FIG. 6A is supplied from the terminal 50 and such a clock signal CK as seen in FIG. 6B is supplied from the terminal 57. Reference characters t.sub.1, t.sub.2 and t.sub.3 each denote a reversal timing of the EFM signal, and in FIG. 6A, the signal Sig0 has a reversal interval of 3 T from t.sub.1 to t.sub.2 and another reversal interval of 4 T from t.sub.2 to t.sub.3. Operation when the signal Sig0 is such as just described will be described below.
The signal Sig0 is first supplied directly to the terminal 51. As seen from FIG. 6J, the signal Sig0 and the control signal Sig1 are the same signal.
Further, the signal Sig0 is logically inverted by the inverter IV.sub.1 and supplied as the control signal Sig2 to the terminal 52. The control signal Sig2 is such a control signal as seen from FIG. 6K.
The inverter IV.sub.2, the flip-flop FF.sub.1 and the AND gate A.sub.1 function as a falling edge detection circuit, and the signal Sig0 is supplied to the inverter IV.sub.2 and the D terminal of the flip-flop FF.sub.1. The flip-flop FF.sub.1 performs a latching operation in response to the clock signal CK and outputs such a Q output as shown in FIG. 6C. The output of the inverter IV.sub.2 exhibits a waveform similar to that of the control signal Sig2 of FIG. 6K. The AND gate A.sub.1 performs AND-operation for the Q output of the flip-flop FF.sub.1 and the output of the inverter IV.sub.2, and the output thereof is shown in FIG. 6D. As seen from FIG. 6D, the AND output provides a falling edge detection pulse outputted in response to each falling edge of the signal Sig0. The falling edge detection pulse is supplied to the AND gate A.sub.4 and is also supplied to the AND gate A.sub.5 byway of the inverter IV.sub.6.
The signal Sig0 is inverted by the inverter IV.sub.4 and supplied to the AND gate A.sub.5.
Meanwhile, the inverter IV.sub.3, the flip-flop FF.sub.2 and the AND gate A.sub.2 function as a rising edge detection circuit, and the signal Sig0 is supplied, after being inverted by the inverter IV.sub.1, to the inverter IV.sub.3 and the D terminal of the flip-flop FF.sub.2. The flip-flop FF.sub.2 performs a latching operation in response to the clock signal CK and provides such a Q output as shown in FIG. 6E. The output of the inverter IV.sub.3 exhibits a waveform similar to that of the control signal Sig1 of FIG. 6J. The AND gate A.sub.2 performs AND-operation for the Q output of the flip-flop FF.sub.2 and the output of the inverter IV.sub.3 and provides a rising edge detection pulse which is outputted in response to each rising edge of the signal Sig0 as seen from FIG. 6F. The rising edge detection pulse is supplied to the AND gate A.sub.6 and is also supplied to the AND gate A.sub.7 by way of the inverter IV.sub.7.
The signal Sig0 is being inverted, after inverted by the inverter IV.sub.1, by the inverter IV.sub.5 again and supplied to the AND gate A.sub.7.
The delay circuit DL.sub.1 delays the clock signal CK to produce a delayed clock signal CK.sub.D1 of FIG. 6G. The delay circuit DL.sub.2 delays the delayed clock signal CK.sub.D1 to produce another delayed clock signal CKD2 of FIG. 6H. The delayed clock signal CK.sub.D1 and the delayed clock signal CK.sub.D2 are supplied to the AND gate A.sub.3 so that a reference pulse signal illustrated in FIG. 6I is produced by the AND gate A.sub.3. The reference pulse signal is supplied to the AND gates A.sub.4, A.sub.5, A.sub.6 and A.sub.7.
The AND gate A.sub.4 performs AND-operation for the falling edge detection pulse signal from the AND gate A.sub.1 and the reference pulse signal from the AND gate A.sub.3 to produce the control signal Sig3 as shown in FIG. 6L. The control signal Sig3 is outputted from the terminal 53.
The AND gate A.sub.6 performs AND-operation for the rising edge detection pulse signal from the AND gate A.sub.2 and the reference pulse signal from the AND gate A.sub.3 to produce the control signal Sig4 as shown in FIG. 6M. The control signal Sig4 is outputted from the terminal 54.
The AND gate A.sub.5 performs AND-operation for the output of the inverter IV.sub.4, the output of the inverter IV.sub.6 and the reference pulse signal and produces the control signal Sig5 as shown in FIG. 6N. The control signal Sig5 is outputted from the terminal 55.
The AND gate A.sub.7 performs AND-operation for the output of the inverter IV.sub.5, the output of the inverter IV.sub.7 and the reference pulse signal to produce the control signal Sig6 as shown in FIG. 6O. The control signal Sig6 is outputted from the terminal 56.
The control signals Sig1 to Sig6 produced in such a manner as described above are supplied as control pulse signals to the switching elements SW.sub.1 to SW.sub.6 of the magnetic head driving circuit 16 of FIG. 4, respectively. Operation of the magnetic head driving circuit 16 based on the control signals Sig1 to Sig6 will be described below. It is to be noted that the description of the operation is given in connection with the points of time t.sub.1 and t.sub.2 between which the EFM signal exhibits the minimum reversal interval of 3T.
Signals are possibly outputted with a "H" level from the control signal production circuit 15P within a period within which the EFM signal (=Sig1) exhibits a "L" level. These signals are the control signals Sig3 and Sig5 as apparently seen from FIGS. 6L and 6N. In particular, with the period, in the magnetic head driving circuit 16, principally the switching elements SW.sub.3 and SW.sub.5 operate to control the electric current to the coil 6L.
The magnetic head driving circuit 16 of FIG. 4 upon reversal of the EFM signal can be represented as such an equivalent circuit as shown in FIG. 7.
Referring to FIG. 7, it is assumed that the switch 22 of FIG. 3 is connected at the N terminal thereof and the magnetic head driving system is operating at the normal transfer rate. In this instance, T=230 nsec. FIGS. 8A to 8E show timing charts of the control signals Sig1, Sig3 and Sig5, the head current Ih flowing through the coil 6L and the voltage Vh.sub.1 at the head terminal h.sub.1.
The peak value of the head current Ih is approximately 0.5 A, and +V of the waveform diagram of the head terminal voltage Vh.sub.1 is approximately +5 V and -V is approximately -45 V.
Transition of the head current Ih and the head terminal voltage Vh.sub.1 will be described beginning with the position of a rising edge of the control signal Sig1.
In a condition immediately prior to a signal reversal (immediately prior to the point of time t.sub.1), that is, at a timing of the "H" level immediately before the control signal Sig1 changes to the "L" level, as can be seen apparently from FIGS. 6J to 6O, the control signals Sig2 to Sig5 exhibits the "L" level while the control signal Sig6 exhibits the "H" level. Consequently, the switching elements SW.sub.1 and SW.sub.6 exhibit an on-state while the other switching elements exhibit an off-state. Thus, in the magnetic head driving circuit 16, an electric current flows along a path of +V.fwdarw.switching element SW.sub.1 .fwdarw.head terminal h.sub.1 .fwdarw.coil 6L .fwdarw.head terminal h.sub.2 .fwdarw.switching element SW.sub.6 .fwdarw.ground (refer to FIG. 4). In the case of the present example, it is assumed that an electric current of approximately 0.5 A flows in the direction of the head terminal h.sub.1 .fwdarw.h.sub.2.
Thereafter, at the point of time t.sub.1, the control signal Sig1 is reversed to the "L" level while the control signal Sig2 is reverted to the "H" signal. From this point of time, the waveforms vary as seen in FIGS. 8A to 8E. This will be described below with reference to an equivalent circuit shown in FIG. 7.
First, at the reversal point of time t1, the switching elements SW.sub.1, SW.sub.3 and SW.sub.5 are all off, and the head terminal h.sub.1 is disconnected from any voltage source. Meanwhile, since the switching element SW.sub.2 is on (not shown), the head terminal h.sub.2 is fixed to the +V voltage as can be seen from FIG. 7.
Movement of charge is governed by an electromotive force, produced by an inductance of the coil 6L, which allows charge to flow in the direction of the head terminal h.sub.1 .fwdarw.h.sub.2. Consequently, an operation is performed in a direction in which charge is sucked from the head terminal h.sub.1 and discharged to the terminal of the head terminal h.sub.2. Since the head terminal h.sub.2 is fixed to the +V voltage, the charge is circulated back to the +V voltage source (positive dc power source 16a) side.
Since the head terminal h.sub.1 side is disconnected from all of the voltage sources, it sucks charge from a small floating capacitance. Accordingly, the voltage Vh.sub.1 of the head terminal h.sub.1 drops rapidly. As the voltage drop proceeds, the coil current Ih decreases little by little. Thus, an operation which can be seen from a t.sub.A period of FIG. 8E is performed.
The voltage drop described above reaches the -V potential and is fixed thereby the voltage source for -V by way of the diode D.sub.1. Within a period after the -V potential is reached until the switching element SW.sub.3 is turned on by the control signal Sig3, that is, within a t.sub.B period of FIG. 8E, charge moves from the -V power source (negative dc power source 16b) to the head terminal h.sub.1 side by way of the diode D.sub.1.
Thereafter, when the control signal Sig3 changes to the "H" level and the switching element SW.sub.3 is turned on, the head terminal h.sub.1 is short-circuited to the -V power source (negative dc power source 16b). Consequently, the voltage Vh.sub.1 of the head terminal h.sub.1 is fixed to -V as seen within a t.sub.c period of FIG. 8E. By the operation described above, the head current Ih exhibits such a variation as seen in FIG. 8D. It is understood that the direction of the head current Ih flowing through the coil 6L is changed over in response to the reversal of the EFM signal (=Sig1).
Thereafter, when the control signal Sig3 changes to the "L" level to turn off the switching element SW.sub.3 so that the head terminal h.sub.1 is disconnected from the power sources, charge moves to the head terminal h.sub.1 side due to an electromotive force in the direction of the head terminal h.sub.2 .fwdarw.h.sub.1 produced by the inductance L of the coil 6L. Consequently, the voltage Vh.sub.1 of the head terminal h.sub.1 approaches +V promptly. Thereafter, the head current Ih decreases gradually. However, since the switching element SW.sub.5 is turned on by the control signal Sig5 and the head terminal h.sub.1 is grounded, the head current Ih thereafter increases again with a slope which depends upon a potential difference between the head terminals h.sub.1 and h.sub.2.
In particular, during the period in which the control signal Sig1 remains at the "L" level after the control signal Sig3 is turned off, the control signal Sig5 is supplied at a required timing so that the head current Ih is kept substantially fixed as seen from FIG. 8D.
By the operations described above, as seen from FIGS. 8A to 8E, within the period of t.sub.1 to t.sub.2, i.e. during a duration of 3 T, an electric current flows in the direction of the head terminal h.sub.2 .fwdarw.h.sub.1 in response to the EFM signal of the "L" level, that is, in response to the control signal Sig1, and a magnetic field is generated from the magnetic head 6 in accordance with the direction of the electric current.
Further, within the period from t.sub.2 to t.sub.3 shown in FIGS. 6J, 6K, 6M and 6O, an electric current flows in the direction of the head terminal h.sub.1 .fwdarw.h.sub.2 by similar operations by the control signals Sig1, Sig2, Sig4 and Sig6, and within this period of 4T, a magnetic field is generated from the magnetic head 6 in accordance with the direction of the electric current.
Since the inductance L of the coil of a magnetic head for practical use is substantially fixed, the rise time (t.sub.A in FIGS. 8A to 8E) is fixed. This can be calculated by the following expressions.
In the following, a time until charge of the coil is discharged is calculated approximately. EQU V=-(d.PHI./dt) (1) EQU .PHI.=Li (2)
From the expressions (1) and (2), EQU V=-L(di/dt) (3)
(wherein L does not vary with respect to time).
Here, the expression (3) can be represented as EQU V=-L(.DELTA.i/.DELTA.t) (4)
Here, the following values are substituted into the expression (4).
V is V=(-V)-(+V), and it is assumed that, with regard to the magnetic head driving circuit 16, V=-45-5 =-50 V. Further, it is assumed that L=5.times.10.sup.-6 (H), and .DELTA.i is the electric current value of 0.5 A exhibited at an initial stage.
Consequently, EQU -50=-5.times.10.sup.-6 .times.0.5/.DELTA.t
and therefore, EQU .DELTA.t=0.5.times.10.sup.-7 (sec)=50 nsec
Consequently, the rise time t.sub.A is approximately 50 nsec.
As an error factor other than that described above, it is considered that the voltage V produced by a magnetic head is lower than -50 V and it requires a longer time than 50 nsec to discharge the charge. Meanwhile, since t.sub.A is a time required to reach -50 V, it is smaller than the value (discharging time of the charge). Accordingly, the two factors cancel each other, and actually the rise time t.sub.A can be approximated to 50 nsec.
A recording operation at a rate twice that of with the construction of the magnetic head driving circuit 16 described above will be examined. In this instance, the switch 22 of FIG. 3 is connected to the F terminal side thereof, and a clock signal having a frequency equal to twice that in a normal operation is supplied as the processing clock signal CK. In this instance, the control signal production circuit 15P, the magnetic head driving circuit 16 and the magnetic head 6 are used as they are.
Timing charts upon a recording operation at the high rate are shown in FIGS. 9A to 9E.
As can be seen by comparison with FIGS. 8A to 8E, the absolute time of, for example, the period of 3 T is AT/2 in FIGS. 9A to 9E with respect to the time illustrated in FIGS. 8A to 8E. As seen from FIGS. 9A to 9E, the control signals Sig1, Sig3 and Sig5 are pulse signals whose time base is 1/2 that in the case of FIGS. 8A to 8E (T.apprxeq.115 nsec).
Meanwhile, the rise time t.sub.A is the same as that at the normal rate in the case of FIGS. 8A to 8E because it relies upon the coil 6L and the magnetic head driving circuit 16. Due to the fact that the rise time t.sub.A is the same, in the case of FIGS. 9A to 9E, the t.sub.B period, that is, the period after the voltage Vh.sub.1 reaches -V until the control signal Sig3 changes to the "H" level, is very short. In this instance, the time from a falling edge of the control signal Sig1 to a rising edge of the control signal Sig3 is approximately 58 nsec and is only a little longer than the rise time t.sub.A of approximately 50 nsec.
The effect of the fact that the period t.sub.B becomes short is, upon the head current Ih, merely that the amplitude decreases a little, and does not matter in practical use. In other words, it is possible to perform a recording operation at twice the rate while the construction described above is maintained.
However, where the magnetic head driving system described above is applied for computer data or the like, recording of a further high speed is demanded. Actually, if the rate in audio applications is considered a normal rate, it is demanded to realize a recording operation of a rate higher than three times the normal rate or more.
Here, a case is examined wherein a clock signal of a rate equal to three times the normal rate is outputted from the clock frequency variation section 21 of FIG. 3 and supplied to the encoder 14 and the control signal production circuit 15P by way of the F terminal of the switch 22 so that an operation at the three time transfer rate is performed
Timing charts of the operation of the magnetic head driving circuit 16 at the three time rate are shown in FIGS. 10A to 10D.
In this instance, as can be seen from comparison with FIGS. 8A to 8E, the absolute time of, for example, the period of 3 T is reduced to AT/3, and as seen from FIGS. 10A to 10D, the control signals Sig1, Sig3 and Sig5 become pulse signals whose time base is reduced to 1/3 comparing with that in FIGS. 8A to 8E (T.apprxeq.78 nsec).
Since the time from a falling edge of the control signal Sig1 to a rising edge of the control signal Sig3 is approximately (1/2)T, it is approximately 39 nsec.
However, the rise time t.sub.A remains approximately 50 nsec and does not exhibit a variation from that at the normal rate shown in FIGS. 8A to BE.
In other words, as can be seen from FIGS. 10A to 10D, at a point of time at which the control signal Sig3 rises, the voltage Vh.sub.1 of the head terminal h.sub.1 does not reach the -V potential as yet.
Consequently, the energy given by the product of .DELTA.V which is the difference between the voltage Vh.sub.1 and the -V potential and the head current Ih when the control signal Sig3 changes to the "H" level and the switching element SW.sub.3 is turned on is processed by the switching element SW.sub.3. This signifies that the construction by a high speed switching element is impossible. In particular, in the condition of the rate up to twice the normal rate, since, at the point of time of a rising edge of the control signal Sig3, .DELTA.V.apprxeq.0 and the energy to be processed .apprxeq.0, the construction by a high speed switching element is impossible.
Thus, the conventional magnetic head driving system of the construction described above cannot be applied when a high speed operation of three or more times a normal rate is intended.